1. Technical Field
The present disclosure relates to a duty cycle protection circuit and to a method of adjusting the duty cycle of a clock signal.
2. Discussion of the Related Art
Clock repeaters (such as buffers or inverters), are used when a clock signal is to be transmitted across an integrated circuit. Clock repeaters boost the clock signal, thereby compensating for attenuation in the transmission line.
In some situations where the clock signal is transmitted over particularly long distances, for example of 10 mm or more, the number of clock repeaters present in the clock path can lead to distortion of the clock signal. In particular, local process variations and power supply noise can lead to asymmetry between the delay that the rising and falling clock transitions are subjected to by the clock repeaters, causing the duty cycle to be distorted. In extreme cases, such a duty cycle distortion over the length of the clock transmission line can lead to the clock signal becoming stuck at a logic low or logic high value, i.e. the clock signal no longer toggles.
There is a need in the art for circuitry to address the above problem of duty cycle distortion.